1. Field of the Invention
The present invention relates to an apparatus for communications, in particular, an apparatus for communications preferably using for a demodulation apparatus demodulating signals quadrature modulated.
2. Description of the Related Art
The quadrature amplitude modulation/demodulation is known as modulation/demodulation technology, which is used for signal conveyance in the communications such as CATV (cable television), satellite communications, multi-channel radio communications. FIG. 9 is a block diagram showing a configuration of a demodulator for demodulating quadrature amplitude modulation wave (modulated signal) in the prior art. As shown in FIG. 9, the demodulator is comprised of an RF unit 11, a MIX unit 12, A/D converters 13a, 13b, a rotator (AFC: Auto Frequency Control) 14, interpolators 91a, 91b, a rotator (CR: Carrier Recovery) 16, low pass filters (LPFs) 17a, 17b, a clock (CLK) phase error operator 18, and a decoder 19.
A modulated signal inputted from a cable or an antenna is performed for frequency conversion in the RF unit 11, so that its frequency is converted into the frequency possibly to demodulate. Subsequently, at the MIX unit 12, the signal is quadrature demodulated into base band signals as I/Q axes (hereafter, I axis is called as “I channel”, Q axis is called as “Q channel”), which are digitized by the A/D converters 13a, 13b. 
That is, the modulated wave, which is frequency converted by the RF unit 11, is quadrature demodulated into the signals corresponding to the phase axes of I channel as in-phase and Q channel as quadrature-phase, and analog formatted I channel and Q channel signals are outputted. The analog formatted I channel signal is converted into a digital formatted I channel signal by the A/D converter 13a, and similarly, the analog formatted Q channel signal is converted into a digital formatted Q channel signal by the A/D converter 13b. 
In addition, the A/D converters 13a, 13b may be arranged different locations from those in FIG. 9 depending upon a processing method. For example, if they are arranged in front of the quadrature demodulation i.e. MIX unit 12, the quadrature demodulation within the MIX unit 12 will become digital process.
The digital data of I/Q channels respectively which are outputted from the A/D converters 13a, 13b are synchronized with carrier. This process is performed by shifting frequency in the rotators 14 and 16; roughly adjusting of coarse adjustment in the rotator (AFC) 14 and perfectly synchronizing of fine adjustment in the rotator (CR) 16. However, if the deviation of frequency is small, the process in the rotator (AFC) 14 may be omitted.
Since sampling in the A/D converters 13a and 13b is performed by using clock signal Fclk1 a synchronized to clock signal Fclk2 which is synchronized with clock signal of the transmission side, in order to restore digital data from the demodulated base band signals of I/Q channels, it is necessary to provide synchronization for sampling timing, which is generally called clock synchronization. FIG. 9 illustrates a configuration which is not for synchronization between the clock signal Fclk1 of sampling timing and data, but for synchronization through adjusting phase of data, and which creates a signal of a phase position obtaining data thereof, with an interpolation process through the interpolators 91a and 91b in order to synchronize the phase of the data. The created data become those synchronizing with the timing Fclk2, which is synchronized with the clock signal of the transmission side.
The base band signals of I/Q channels phase adjusted by the interpolators 91a and 91b are finally synchronized with the carrier by the rotator (CR) 16, and is wave-shaping through low pass filters (LPFs) 17a and 17b, which are called roll-off filters; thereby signals are created. In general, because of processing such as error correcting and framing on the digital data, they will be decoded by the decoder (DEC) 19 as necessary.
The interpolating operation through the interpolators 91a and 91b shown in FIG. 9 will be described, referring to FIG. 10. In FIG. 10, DTI is input data, which is a sine wave in the figure for easy understanding of it. STA1 to STA4 shown by broken lines are sampling timings for the input data DTI based on the clock signal Fclk1, and STB1 to STB4 shown by one doted chain lines are original sampling timings based on the clock signal Fclk2.
In order to obtain signals at positions where are original sampling timings from the signals sampled by the A/D converters 13a and 13b, original data sequence ID1 to ID4 at desirable sampling timings STB1 to STB4 are calculated and produced, from each of output data sequence SD1 to SD4 of the A/D converters 13a and 13b at sampling timings STA1 to STA4. Wherein, information relating to shifting phases Δt1 to Δt4 are outputted as phase error information PSI from the clock phase error operator 18 shown in FIG. 9.
FIG. 11 is a block diagram showing a configuration of the clock phase error operator 18. The clock phase error operator 18 comprises a clock phase error extractor 111, a phase comparator (PD) 112, a loop filter (LPF) 113, and an oscillator (NCO) 114.
A phase error is extracted from inputted I/Q channel data through the clock phase error extractor 111. The extracted phase error is compared with output timing of the oscillator 114 by the phase comparator 112. With processing of the clock phase error extractor 111 and the phase comparator 112, the phase error Δt is calculated.
Then, the comparison result at the phase comparator 112 is integrated (smoothed out) by the loop filter 113, whereby the oscillator 114 is controlled on the basis of the integration result. That is, a PLL (Phase Locked Loop) is composed of the phase comparator 112, the loop filter 113, and the oscillator 114. Though the oscillator 114 outputs the timing of clock signal Fclk2, actually it will inform the interpolators 91a and 91b about the phase difference from the clock signal Fclk1 as phase error information.
In the following patent document 1, detecting a symbol timing error from an output signal of a matching filter through a timing error detector, and changing tap coefficients of the matching filter based on the detected timing error information are described.
[Patent Document 1] U.S. Pat. No. 5,872,818